Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a signal generating circuit of the semiconductor device which generates a number of test mode selecting signals for performing a test during an operational mode, and further generates signals at a normal operational mode.
Description of Prior Art
In general, operations of semiconductor devices can be classified into normal and test modes. Test modes are subdivided into a plurality of test items, for which respective tests are performed to determine whether a product is good or defective.
In order to get the semiconductor device ready to test each test item, it is necessary to have test mode selecting signals generated internally within the semiconductor device to set up the test mode. For this purpose, a test mode selecting circuit is constructed with a predetermined number of pins among address or data pins of the semiconductor device, which are used as test mode selecting pins for buffering and decoding signals transmitted to the pins, to thereby generate test mode selecting signals for testing a plurality of test items.
The conventional test mode selecting circuit of the semiconductor device can only generate n2 test mode selecting signals, where, n denotes the number of pins. For example, if the number of test items to test at the test operational mode is 8, 3 test mode selecting pins are required. If more test items are required, more test mode selecting pins should be allocated.
The same is also true for internally generated signals at the normal operational mode. Their maximum number is 2, where n denotes the number of pins. Therefore, if internally generated signals are required, more pins are also required for the operation.
In other words, in semiconductor devices the number of pins allocated for testing should increase when the number of signals to be internally generated increases, whether at test or normal operational modes. This is a problem, because semiconductor devices have the tendency of increasing integration, which decreases the size of the chip. Any increase in the number of pins limits the efforts to reduce the size of the chip.
FIG. 1 is a block diagram for illustrating a conventional test mode selecting circuit of a semiconductor device, which has been already disclosed in U.S. Pat. No. 5,036,272, which is hereby incorporated by reference.
There are input pins 10, 14-1, 14-2, 14-3, 14-4, buffers 12, 16-1, 16-2, 16-3, 16-4, a high voltage sensing circuit 18, decoders 20, 22 and a mode selecting circuit 24 at the block diagram in FIG. 1. As can be seen, a predetermined number of pins of the semiconductor device used for normal operations at the normal operational mode are used as pins for generating test mode selecting signals at the test operational mode.
Since there are only four input pins 14-1, 14-2, 14-3, 14-4, the conventional test mode selecting signal generating circuit shown in FIG. 1 can only generate up to 16 test mode selecting signals. This, in turn, limits the number of test items.
As more test items are required, more pins in the circuit are required. Therefore, there still remains a problem in the conventional test mode selecting signal generating circuit, in that the increase in the number of pins to be used at the test operational mode can not be restricted, in spite of reduction in the size of a chip.
The present invention recognizes that the prior art was so limited because it only allowed each test input pin to receive a signal of only two possible values (high and low). The present invention provides a device and a method that allows more values for each of the input pins, and therefore permits more test modes without requiring more pins.
The present invention therefore provides a signal generating circuit of a semiconductor device, and a method for invoking test modes in the semiconductor device.
The signal generating circuit of the device of the invention includes n input test pins for receiving respective coded input signals. At least one of the input signals is coded in more than two possible levels, such as 3 levels or four levels.
The device further includes an indicator signal generators, each coupled respectively with an associated input test pin. Each indicator signal generator generates indicator signals in response to the coded input signal received by its associated input test pin. The indicator signals are of only two levels.
A decoder receives the indicator signals to produce decoded signals, and a mode selecting circuit generates mode selecting signals with the decoded signals responsive to mode setting signals.
The indicator signal generators preferably include a buffer outputting a regular signal, indicative of whether the associated input signal has an ordinary low level, a first higher level voltage detector for outputting a higher first level signal indicative of whether the associated input signal has a first extra high level higher than the ordinary low level, and a scrambling circuit for producing, in response to the regular signal and to the higher first level signal, a control signal indicative of whether the associated input signal has an ordinary high level higher than the ordinary low level and lower than the first extra high level.
If more than three levels are used, the indicator signal generators further include a second higher level voltage detector for outputting a higher second level signal indicative of whether the associated input signal has a second extra high level higher than the first extra high level.
The method of the invention is for invoking a test mode in a circuit of a semiconductor device. The method includes applying coded input signals to input test terminals of the circuit, where at least one of the input signals has more than two possible levels, then generating two-level indicator signals in response to the coded input signals, and decoding the indicator signals to generate decoded signals.
These and other features and advantages of the present invention will be understood from the Detailed Description and the drawings.